SC424MLTRT【PDF 17/29 页】IC REG DL BUCK/LINEAR 28MLPQ

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Sheet目录46

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SC414/SC424

Because the on-times are forced to occur at intervals no

greater than 40約, the frequency will not fall far below

25kHz. Figure 5 shows ultrasonic power-save operation.

FB Ripple

Voltage (V

)

FB threshold

(750mV)

Inductor

Current

(0A)

40約 time-out

minimum f

~ 25kHz

After the 40約ec time-out, DL drives high if V

has not reached the FB threshold.

DH On-time is triggered when

reaches the FB Threshold

On-time

)

Figure 5 Ultrasonic Power-save Operation

Power-save Mode Operation (SC424)

The SC424 provides power-save operation at light loads

with no minimum operating frequency. With power-save

enabled, the internal zero crossing comparator monitors

the inductor current via the voltage across the low-side

MOSFET during the off -time. If the inductor current falls to

zero for 8 consecutive switching cycles, the controller

enters power-save operation. It will turn off the low-side

MOSFET on each subsequent cycle provided that the

current crosses zero. At this time both MOSFETs remain

off until V

drops to the 750mV threshold. Because the

MOSFETs are off , the load is supplied by the output capaci-

tor. If the inductor current does not reach zero on any

switching cycle, the controller immediately exits power-

save and returns to forced continuous mode. Figure 6

shows power-save operation at light loads.

FB Ripple

Voltage

)

FB threshold

Inductor

Current

Zero (0A)

DH On-time is triggered when

reaches the FB Threshold.

(750mV)

On-time (T

)

DL drives high when on-time is completed.

DL remains high until inductor current reaches zero.

Dead time varies

according to load

Figure 6 Power-save Operation

Smart Power-save Protection

Active loads may leak current from a higher voltage into

the switcher output. Under light load conditions with

power-save enabled, this can force V

OUT

to slowly rise and

reach the over-voltage threshold, resulting in a hard shut-

down. Smart power-save prevents this condition. When

the FB voltage exceeds 10% above nominal (exceeds

825mV), the device immediately disables power-save, and

DL drives high to turn on the low-side MOSFET. This draws

current from V

OUT

through the inductor and causes V

OUT

fall. When V

drops back to the 750mV trip point, a normal

switching cycle begins. This method prevents a hard

OVP shutdown and also cycles energy from V

OUT

back to

. It also minimizes operating power by avoiding forced

conduction mode operation. Figure 7 shows typical wave-

forms for the Smart Power-save feature.

SmartDrive

For each DH pulse, the DH driver initially turns on the

high-side MOSFET at a slower speed, allowing a softer,

smooth turn-off of the low-side diode. Once the DH node

is high and the LX voltage has risen 1V above PGND, the

SmartDrive circuit automatically drives the high-side

MOSFET on at a rapid rate. This technique reduces ringing

while maintaining high efficiency and also avoids the

need for snubbers or series resistors in the gate drive.

Applications Information (continued)

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